1. Field of the Invention
The present invention relates to a technique for suppressing coupling noise occurring between bit lines connected to memory cells of a semiconductor memory to prevent malfunction of the semiconductor memory.
2. Description of the Related Art
FIG. 1 shows a schematic view of a memory cell array of a typical DRAM. In this example, four-bit data DQ0–3 are inputted to or outputted from the memory cell array in one operation.
The memory cell array has a memory cell unit MEM, word decoders WD located on opposite sides (left and right of the figure) of the memory cell unit MEM, sense amplifiers SA located on the other opposite sides (upper and lower of the figure) thereof, and cross regions CRS located at the four corners thereof. The memory cell unit MEM includes a plurality of memory cells MC arranged in a matrix.
The word decoders WD each activate (select) one of word lines WL in accordance with a row address. The word lines WL are connected to the gates of the transfer transistors of the memory cells MC. The activation of a word line allows data stored in the capacitors of the associated memory cells MC to be read out onto the respective bit lines BL (or /BL).
The sense amplifiers SA, which are connected to the respective complementary pairs of bit lines BL and /BL, amplify the data read onto the bit lines BL (or /BL). In the cross regions CRS, there are located switches of data buses (not shown); contacts for switching the wiring layers of the data buses; buffers of control signal lines of the sense amplifiers SA; and so on.
FIG. 2 illustrates read and write operations of the DRAM described above. Hereafter, the names of signals may be accompanied by the same reference designations as the signal lines through which those signals are transferred; for example, the signal transferred through a word line WL will be referred to as word line signal WL.
During a read operation, a given word line signal WL (e.g., WL shown by a thick line in FIG. 1) changes, in accordance with a corresponding row address, to a high level, which turns on the transfer transistors of the memory cells MC connected to the word line WL. The data held by the memory cells MC (high levels in this example) are transferred to the respective bit lines BL, so that the voltages of those bit lines BL go up (FIG. 2(a)). It should be appreciated that before the read operation, the bit lines BL and /BL are set to a precharging voltage that is a reset voltage.
Next, a latch enable signal LE that is a control signal for controlling the sense amplifiers SA changes to a high level, causing all the sense amplifiers SA shown in FIG. 1 to commence their operations (FIG. 2(b)). These operations of the sense amplifiers SA amplify the voltage differences of the pairs of bit lines BL and /BL (FIG. 2(c)). That is, the data of all the memory cells connected to the word line WL are amplified.
Next, a given column selecting signal CL changes, in accordance with a corresponding column address, to a high level (FIG. 2(d)), which turns on column switches (not shown) connected to the four sense amplifiers SA corresponding to data signals DQ0–3. Out of the pairs of bit lines BL and /BL on which the read data have been amplified, the four pairs of bit lines BL and /BL selected by the column address (e.g., the bit lines BL and /BL shown by thick lines in FIG. 1) are connected to the associated data buses (not shown). Then, the four-bit read data DQ0–3 are outputted to the data buses. Thereafter, the column selecting signal CL, word line signal WL and latch enable signal LE sequentially change to their respective low levels, so that the read operation of the memory cell array is completed (FIG. 2 (e)).
It should be appreciated that the data read from the memory cells MC and amplified by the sense amplifiers SA are written into the memory cells MC again. An interval designated by HLD in FIG. 2 is a hold interval required to hold the data on the bit lines BL and /BL so as to rewrite the data into the memory cells MC.
During a write operation, as during the read operation, a given word line signal WL changes to a high level, and the data held in the associated memory cells MC (in this example, high levels) are transferred to the respective associated bit lines BL (FIG. 2(f)). Next, a latch enable signal LE changes to a high level, and the voltage differences of the pairs of bit lines BL and /BL are amplified (FIG. 2(g)).
During the amplifying operation of the sense amplifiers SA, write data are supplied to the pairs of bit lines BL and /BL selected by a column address (e.g., the bit lines BL and /BL shown by the thick lines in FIG. 1). In this example, the data held in the corresponding memory cells MC are different from the write data therein. For this reason, the data amplified by the corresponding sense amplifiers SA are inverted in accordance with the write data (in this example, low levels) (FIG. 2(h)). That is, the write operation requires an inverting time TR that is not existent in the read operation. The write data are fully amplified by the corresponding sense amplifiers SA and then written into the corresponding memory cells MC.
With respect to the memory cells MC into which data are not written during the write operation, the data read therefrom to the bit lines BL and /BL are rewritten thereinto (a refreshing operation). That is, the data on pairs of the bit lines BL and /BL that are not selected by the column address are amplified by the corresponding sense amplifiers SA and then rewritten into the corresponding memory cells MC.
Thereafter, the column selecting signal CL, word line signal WL and latch enable signal LE sequentially change to their respective low levels, so that the write operation of the memory cell array is completed (FIG. 2(i)). Another interval designated by HLD in FIG. 2 is a hold interval required to hold the data on the bit lines BL and /BL so as to write the data into the memory cells MC.
It should be appreciated that when the data held in the memory cells MC are inverted in accordance with the write data during the write operation, the voltages of the corresponding pairs of bit lines BL and /BL change largely, as shown in FIG. 2. This voltage change is propagated, as coupling noise, to the adjacent other bit lines BL and /BL. The smaller the wiring pitch of the bit lines BL and /BL, and the larger the voltage differences of the pairs of bit lines BL and /BL, the greater the affections on the adjacent bit lines BL and /BL.
Recently, finer patternings of semiconductor processes have permitted to provide smaller-sized memory cells. Accordingly, the wiring pitches of the word lines WL and bit lines BL and /BL have been the smaller, and hence the coupling capacitances have become the larger. Therefore, the affections of the coupling noise on the adjacent bit lines BL and /BL have been apt to be the larger.
In the DRAM described above, during the write operation, data are written into only a part of the selected memory cells MC (in the example of FIG. 1, four bits), while the original data are rewritten into the remaining memory cells MC. Consequently, the pairs of bit lines BL and /BL that are adjacent to the pairs of bit lines BL and /BL through which the write data are transferred (the pairs of bit lines BL and /BL shown by the thick lines in FIG. 1) are the most likely to receive coupling noise caused by the write data. Consequently, there is a possibility of destruction of the data held in the memory cells in the rewrite operation.
During the write operation, the write data are supplied after the data read from the memory cells MC have been amplified to some degree (FIG. 2(g, h)). However, the greater the degree to which the data read from the memory cells MC are amplified, disadvantageously the longer the inverting time TR. In general, the write and read cycle times, which are product specifications, are established as being equal to each other in order that the systems including DRAMs may be easy to use. Thus, when the write operation time is longer, the product specification of cycle time including the read operation (a timing specification) must be established as being accordingly longer.
The sense amplifiers SA must be arranged in accordance with the layouts of the memory cells MC and pairs of bit lines BL and /BL. Accordingly, the width of the layout of the sense amplifiers SA (in the lateral direction of FIG. 1) is apt to become smaller as the patternings of the semiconductor processes become finer. Accordingly, the shape of the layout of the sense amplifiers SA is narrower and longer in the vertical direction of FIG. 1 so that the layout design is difficult. Besides, the cross regions CRS also must be relatively small, so that the layouts of the switches of the data buses and the like are difficult.
The followings are recitations of the prior arts related to the present invention.
Japanese Unexamined Patent Application Publication No. Sho 61-206254 discloses a technique wherein power supply wires are provided between adjacent bit lines so as to prevent malfunction.
Japanese Unexamined Patent Application Publication No. Hei 2-91884 discloses a technique wherein the bit lines adjacent to the ones connected to memory cells to be accessed are fixed to a precharge voltage so as to prevent malfunction.
Japanese Unexamined Patent Application Publication No. 2002-32994 discloses a technique wherein the bit lines adjacent to the ones connected to memory cells to be accessed are grounded so as to prevent malfunction.